1. Field of the Invention
The present invention relates to an on-track detecting circuit for use in a tracking servo apparatus which is used in an optical disk apparatus.
2. Description of Background Information
FIG. 1 generally shows the relationship between pits formed on an optical disk and an output signal obtained by optically reading the pits. In FIG. 1, a portion (a) shows servo byte patterns for a sampled servo in an optical disk apparatus. Each sector of an optical disk consists of, for example, 43 servo blocks. One servo block is constituted by servo bytes of two bytes and subsequent data bytes of 16 bytes. The servo bytes are constructed by: two wobble pits of a third or fourth channel bit and an eighth channel bit of the first byte; and one clock pit of a twelfth channel bit of the second byte. The wobble pits are arranged on the right and left sides of the track center. When a pickup (light spot for information detection) traces the track center, reduction amounts of light amounts in the right and left wobble pits are equalized. When the trace position is deviated to the right or left from the track center, a tracking error signal is formed from a difference (level difference of an RF signal shown by a portion (c) in FIG. 1) between the light amounts in the two wobble pits in correspondence to the direction and amount of the deviation. The tracking error signal is held for an interval of the subsequent data bytes.
Since the former wobble pit is alternately arranged for the third or fourth channel bit every 16 tracks, an interval between the two wobble pits is alternately changed to a longer interval and a shorter interval every 16 tracks. By detecting change in such interval, the number of tracks can be accurately counted (16-track counting) even at the time of a high speed searching.
A distance D between the wobble pit which is located further backward and the clock pit is set to a special length which doesn't appear in the data bytes, so that the distance D can be detected as a synchronization (sync) signal. Various timing signals are formed on the basis of the detected sync signal. A clock signal (a portion (d) in FIG. 1) is formed in correspondence to a detection signal of the clock pit. In mirror surface portion locating at the distance D, a focusing error signal is sampled and is held for an interval of the subsequent data bytes.
In the data byte interval subsequent to such a servo byte interval, data is recorded by pits, in the form of phase change, or by using a magnetooptic method.
Specifically speaking, as shown in FIG. 2, sample and hold (S/H) circuits 3, 4, and 5 for sampling and holding photodetection signals obtained at the timings of the 3- , 4- , and 8-channel clocks are respectively provided. In order to discriminate in which one of the 3- and 4-channels the pit exists, outputs of the sample and hold circuits are led to a comparator 13. An output of the comparator 13 is latched by a latch circuit 17 and the sample and hold output of the channel clock in which the pit exists is selected by a selector 18. A difference between a selection output of the selector 18 and the sample and hold output in the 8-channel clock is detected by a subtractor 19, thereby obtaining the tracking error signal.
In such a tracking servo, when a tracking servo loop is closed, a servo is applied so that the tracking error signal is equal to zero. The timing at which the tracking error signal is nearly equal to zero when opening the tracking servo loop, however, exists in two cases of the timings of "on track" and "between tracks". When the tracking servo loop is closed at a wrong timing, therefore, there occurs a possibility that a laser beam is not focused onto the track. An on-track detecting circuit for judging whether the tracking loop can be closed or not is consequently necessary.
As an on-track detecting method in the on-track detecting circuit, in the optical disk of the sample servo format, only the clock pit exits on the track at the timing of the 12-channel clock in the second servo byte in the servo block as mentioned above. Since an amplitude value of the clock pit is larger than that between the tracks, by comparing those amplitude values, it is possible to discriminate whether the clock pit is an on-track state or not. The amplitude value of the clock pit is sampled a plurality of times, accordingly, the maximum and minimum amplitude values are obtained and the half of the sum of those values is set to a slice level. When the above amplitude value is larger than the slice level, it is judged as an on-track position.
FIG. 3 shows a more detailed circuit obtained by forming a digital IC from the foregoing tracking error detecting circuit and the on-track detecting circuit. First, the tracking error detecting circuit will be described. After that, the on-track detecting circuit will be described.
Tracking error detecting circuit
In the diagram, an RF signal reproduced from the optical disk or the like is supplied to an A/D converting circuit 1 and is A/D converted. Clocks necessary for the A/D converting operation have been supplied to the A/D converting circuit 1. A digital signal generated from the A/D converting circuit 1 is transmitted to latch circuits 3A to 5A and 6. The latch circuits 3A to 5A correspond to the sample and hold circuits 3 to 5 shown in FIG. 2. A timing signal generating circuit 2 forms a predetermined timing signal synchronously with a trigger signal and the clock which are received and supplies to circuits and means. The timing signals corresponding to the third, fourth, and eighth channel bits of the first byte and the twelfth channel bit of the second byte mentioned above have been supplied to the latch circuits 3A to 5A and 6, respectively. The latch circuits 3A to 5A and 6, therefore, latch the digital signals at timings of the timing signals.
Outputs of the latch circuits 3A and 4A are supplied to the comparator 13. The comparator 13 outputs, for example, a signal of the high level when the output of the latch circuit 3A is larger than the output of the latch circuit 4A and outputs a signal of the low level when the output of the latch circuit 3 is smaller than the output of the latch circuit 4A. The output of the comparator 13 is supplied to a delay flip-flop 17A as a latch circuit, and is latched at a predetermined timing. As mentioned above, the first wobble pit is formed in the third or fourth channel bit. The flip-flop 17A, which corresponds to the latch circuit 17 shown in FIG. 2, therefore, outputs the signal of the high level for a period of time of 16 tracks during which the wobble pit is recorded in the third channel bit and the signal of the low level for a period of time of 16 tracks during which the wobble pit is recorded in the fourth channel bit. That is, by monitoring the output of the flip-flop 17A, 16 tracks can be counted.
The output of the flip-flop 17A is supplied to a selector 18. The selector 18 selects and generates the output of the latch circuit 3 when the signal of the high level is received and the output of the latch circuit 4 when the signal of the low level is received. By such operations, the output having the wobble pit in the outputs of the latch circuits 3A and 4A is selected by the selector 18 and is latched by a latch circuit 7. A timing signal similar to that of the latch circuit 5A has been supplied to the latch circuit 7. As mentioned above, a difference between the value latched by the latch circuit 5A and the value latched by the latch circuit 7 is calculated by a subtracting circuit 19. Since the latch circuits 5 and 7 latch the values in the two wobble pits, a digital tracking error signal is consequently formed by a subtracting circuit 19A which corresponds to the subtractor 19 shown in FIG. 2. The digital tracking error signal that is generated by the subtracting circuit 19 is latched by a latch circuit 8 at a predetermined timing.
An output of the latch circuit 8 is further supplied to a latch circuit 9 and is latched. Adding circuits 21 and 22 add predetermined reference values to an output of the latch circuit 9. A comparing circuit 14 compares the output of the latch circuit 8 and an output of the adding circuit 21. When the former output is larger than the latter one, the comparing circuit 14 generates, for example, a signal of the high level. A comparing circuit 15 similarily compares the output of the latch circuit 8 and an output of the adding circuit 22 and generates the signal of the high level when the former output is smaller than the latter one. That is, what is called a window comparator is constructed by the comparing circuits 14 and 15 and the adding circuits 21 and 22. When a logic circuit 25 receives the signal of the high level from the comparing circuit 14 or 15 or receives an out-of sync signal from a circuit (not shown), the logic circuit 25 controls the latch circuit 9, thereby prohibiting the latching of the output of the latch circuit 8. In this manner, the latch circuit 9 latches the output of the latch circuit 8 when the output of the latch circuit 8 lies within a predetermined reference range and generates the latched value. When the output of the latch circuit 8 is out of the reference range, the latch circuit 9 generates the previously-latched value as it is. The digital tracking error signal generated from the latch circuit 9 is supplied to a D/A converting circuit 24 and is converted to an analog signal and the analog signal is transmitted.
On-track detecting circuit
The on-track detecting circuit will now be described. The output of the latch circuit 9 is supplied to a detecting circuit 26. The detecting circuit 26 detects an inversion (zero-cross) of the polarity of the tracking error signal and generates a detection signal to a circuit (not shown). When the inversion of the polarity is detected, the detecting circuit 26 generates a timing signal to a latch circuit 10 (or 11). When the next inversion of the polarity is detected, the detecting circuit 26 generates the timing signal to the latch circuit 11 (or 10). The latch circuits 10 and 11, accordingly, alternately latch the output of the latch circuit 6 every inversion of the polarity of the tracking error signal. An adding circuit 23 adds outputs of the latch circuits 10 and 11 and generates the mean value. The mean value is latched by a latch circuit 12 at a predetermined timing. Since the latch circuit 6 latches the level at the timing of the clock pit, the latch circuit 12, consequently, latches the means value obtained in a manner such that a clock level when an information detection point traces just on the track and a clock level when the information detection point traces just between the tracks are added and a resultant value is divided by 2. A comparing circuit 16 compares the output of the latch circuit 6 and an output of the latch circuit 12. When the former output is equal to or larger than the latter one, it is regarded that the information detection point is located on the track, so that an on-track signal is generated.
In such an on-track detecting circuit, however, although there is no problem in the case where a carriage holding a pickup for emitting a laser beam moves in the disk radial direction at a very low speed, as the carriage moves at a high speed, the clock pit cannot be always sampled on the track and between the tracks. The number of samples, therefore, decreases and an accurate mean value of the amplitudes of the clock pits cannot be eventually obtained. A case of erroneously recognizing an on-track position consequently occurs.
In such a detecting method, the latch circuits, adding circuits, and the like for detecting the clock pits, sampling a number of amplitude values thereof, and storing those sample values are necessary and the circuit is accordingly complicated, so that it causes an increase in cost.